The present invention relates to a semiconductor-chip mounting substrate with a high degree of reliability of an electrical connection between a substrate and a semiconductor chip such as IC chip, and a method of manufacturing the same.
As a conventional method of surface mounting (flip chip bonding) a semiconductor chip such as IC chips on a substrate, for example, there is a work mounting method disclosed in Japanese Patent Early Publication [kokai] No. 10-199935. In this method, bumps that are projections having electrical conductivity are formed on an IC chip and a substrate, and the bumps of the IC chip are pressed against the bumps of the substrate to cause plastic deformations of the bumps, so that electrical connections therebetween are achieved.
However, in the above method, since a large number of the bumps are formed on the substrate, variations in height of the bumps on the substrate easily increase. In such a case, when the bumps of the substrate are bonded to the bumps of the IC chip, it becomes difficult to provide a constant contact pressure to each of the electrical connections between the bumps. In addition, forming the bumps having the constant height individually on the substrate leads to an extension in production time by a large amount.
Moreover, as the packaging density of IC chips becomes higher, a total number of terminals of the respective IC chip increases. To achieve favorable electrical connections on all of the terminals, it is needed to severely control the flatness of an IC-chip mounting surface of the substrate. However, in actuality, due to a warpage of the substrate after molding, it is difficult to stably supply the substrate with a high level of the flatness. As a result, there is a fear that the reliability of electrical connections in the IC-chip mounting substrate lowers.
On the other hand, when using a resin substrate for MID (molded interconnect device) as the substrate, a coefficient of linear expansion of the semiconductor chip (approximately 4xc3x9710xe2x88x926/xc2x0 C.) is much smaller than that of the substrate (approximately 20xcx9c50xc3x9710xe2x88x926/xc2x0 C.). Because of such a great difference in the coefficient of linear expansion therebetween, a large thermal stress occurs at the interface between the substrate and the semiconductor chip. This thermal stress becomes a cause of further reducing the reliability of the electrical connections between the semiconductor chip and the substrate.
Therefore, a primary object of the present invention is to provide a semiconductor-chip mounting substrate with a high degree of reliability in electrical connection between a substrate and a semiconductor chip.
That is, the semiconductor-chip mounting substrate comprises:
a substrate having at least one projection thereon, which is integrally molded with the substrate;
a first bump obtained by forming a conductive layer on the projection; and
a semiconductor chip having a terminal projecting as a second bump on its surface;
wherein the semiconductor chip is mounted on the substrate such that the first bump contacts the second bump, and the semiconductor-chip mounting substrate comprises a pressure holding means for providing a required contact pressure between the first bump and the second bump.
In the present invention, when integrally molding a plurality of projections with the substrate, it is possible to provide the first bumps with reduced variations in height on the substrate at a time. This brings a considerable decrease in production time and an improvement of production yields of the semiconductor-chip mounting substrate. In addition, even when a level of flatness of a semiconductor-chip mounting surface of the substrate is not so high, and there is a relatively large difference in coefficient of linear expansion between materials of the substrate and the semiconductor chip, the required contact pressure between the first and second bumps is provided and maintained by the pressure holding means. Therefore, it is possible to stably ensure the reliability of the electrical connection between the first and second bumps.
It is preferred that the pressure holding means is a resin material filled and cured in a space between the substrate and the semiconductor chip.
As the pressure holding means, it is also preferred to use a pressure holding member having a first surface adapted to contact a surface opposed to the second bump of the semiconductor chip, and a second surface extending around the first surface. In this case, the substrate has a concave, in which the semiconductor chip can be incorporated. The first bump is integrally molded at a bottom surface of the concave with the substrate. The second surface of the pressure holding member is bonded to the substrate such that the first surface of the pressure holding member pushes the semiconductor chip placed in the concave toward the substrate, to thereby provide the required contact pressure between the first bump and the second bump.
Another object of the present invention is to provide a method of manufacturing a semiconductor-chip mounting substrate. That is, this method comprises the steps of:
providing a substrate having at least one projection thereon, which is integrally molded with said substrate;
forming a conductive layer on the projection to obtain a first bump;
providing a semiconductor chip having a terminal projecting as a second bump on its surface;
pressing the second bump against the first bump under a pressure that is in an elastic deformation range of the first bump and causes a plastic deformation of the second bump, to bring the second bump into intimate contact with the first bump, and
providing the pressure holding means to hold a required contact pressure between the first bump and the second bump under the intimate contact condition.
These and still other objects and advantages will become apparent from preferred embodiments of the present invention described below and the attached drawings.
The present disclosure relates to subject matter contained in Japanese Patent application No. 2000-402818, filed on Dec. 28, 2000, the disclosure of which is expressly incorporated herein by reference in its entirety.